System-on-Chip (SoC) based on FPGA (Field Programmable Gate Array) fused with a processor is an interesting platform. This integrates the processor, the memory, the connection network on a single chip, which causes a lower demand for system power. A typical SoC consists of a 32-bit processor core and many designer-selectable features that allow a fully custom system to be designed, reducing space and power consumption to what is strictly necessary. These functions include memory, bus interfaces, I / O drivers, decoders, and network support. Embedded systems are often used in applications that require responding to external events in real time.
Today many embedded products are built using various chips, making them larger, more expensive and with higher electrical consumption requirements. System on Chip (SoC) have existed for a long time on ASIC (Application Specific Integrated Circuit) boards, but these MPSoCs are very recent, and thanks to their FPGA part and their intrinsic reconfiguration capacity, they allow a large part of the chip to be reconfigured. and therefore the system, eating more and more space from ASICs. In such a way, that more and more companies are turning to the development of embedded SoC systems (FPGA + MP) that make the development and evaluation of the product, as well as its future evolution, reliable, easier and cheaper.
MPSoC: typical diagram. Source: Xilinx.
As we said, MPSoC inclue programmable processors, configurable communication networks inside between processor, FPGA, memories and others configurables cores of periferical and function components. The great advantage of an MPSoC and/or FPGA relative to other devices is the inclusion of configurables powerful IP cores inside (intellectual property cores) that can be configured on the same silicon chip. These IP cores are units of logic designed by an entity that has intellectual property rights over it. The use of these blocks simplifies and speeds up the design of an electronic circuit such as an FPGA or an ASIC. Examples of IP cores are CPUs, UARTs, PCI interfaces and embedded Ethernet controllers such as Hard IP on the FPGA chip.
The purpose of IP cores is to minimize the appearance of problems during the design stage, reduce the time-to-market of the product and reduce the costs involved in developing it. The use of standards favors the portability of these blocks. More complex IPs require software (in the form of APIs).
IP cores can be classified into three large groups, based on their flexibility and portability:
Hard cores: when a core is going to be used on different systems, it must be possible to adapt it without making any changes to it (or almost none). They are therefore very inflexible, but very predictable and reliable when implementing them. They include place and route information. A good example of this type of core are processors and memories.
Firm cores: halfway between the hard cores and the soft cores, they are configurable blocks but they also have some information about the place and route. It has limited flexibility and acceptable predictability in implementation.
Soft cores: they are usually HDL or netlist files (list of logic gates and their respective connections). They are highly flexible, and can be customized specifically for each application. They are very flexible but not very predictable in implementation.
However, FPGA-based implementations and developments are not an easy task, and you may not always have the experience, resources, or time to fulfill your planning.
Our team of engineers specialized in FPGAs and SoC / MPSoC offers you experience and services to develop your product, with the mission of helping you reduce your development cycles. At GENERA Technologies we have a long history helping our clients to convert the signal acquired by the sensor into processed, reliabilted and real-time information in the shortest latency in a wide range of applications and sectors. Contac us.